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Highlights
- The deployment possibilities of low-geometry chips are wide-ranging, from high-performance computing to mobile and handheld devices, real-time processing at the edge, and AI performance.
- The next-generation low-geometry chips will empower leaders to drive transformative growth through the convergence of library creation, material selection, simulation, AI-driven EDA tools, advanced package design, and design for testability.
- As the five focus areas converge over the next few years, industry leaders can unlock the power of low-geometry chips.
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Towards lower nodes
Modern semiconductor chips are being reimagined to meet the demands of intelligent, connected products. These chips must deliver built-in AI capabilities, ultra-low power consumption, and extreme processing speeds while remaining IP-centric and optimized for high-speed performance. IoT, AI, and 5G technologies are at the heart of this transformation, positioning the chip as the core enabler of intelligent systems and everyday experiences.
These advanced silicon chips drive innovation across diverse applications—from automated factories that rely on real-time data and predictive maintenance, intelligent consumer gadgets that adapt to user behaviour, and anomaly detection systems in industrial process control. They also enable smart living solutions for enhanced home comfort, and serve as the backbone of autonomous vehicles, where rapid decision-making and edge processing are critical.
Developing such high-performance, AI-driven chips requires tight collaboration across the semiconductor ecosystem, including IP design houses, EDA tool vendors, fabrication equipment providers, packaging specialists, and testing partners. This integrated approach is essential to delivering the intelligence, efficiency, and speed demanded by next-generation applications.
A paradigm shift
The semiconductor landscape is undergoing a profound transformation, driven by breakthroughs across multiple domains. At the forefront are advanced CPUs and GPUs, built on cutting-edge 3nm and smaller process nodes, delivering exceptional performance for general-purpose and graphics computing. These are closely followed by 5G/6G and RF silicon chips, which enable next-generation wireless connectivity and form the backbone of ultra-fast, low-latency communication networks.
AI/ML accelerator chips are another critical innovation, purpose-built to accelerate artificial intelligence and machine learning workloads. These include custom ASICs tailored for deep learning and edge AI applications, enabling real-time inference and intelligent decision-making at the device level.
A significant leap is seen in photonic and optical interconnect chips, which are revolutionizing data movement in high-performance systems. By replacing or augmenting traditional electrical interconnects with optical pathways, these chips harness the power of light to deliver faster, more efficient data transfer, meeting the surging bandwidth demands of data centers and high-speed computing environments.
In the realm of automotive and edge computing, system-on-chips (SoCs) are driving the evolution of autonomous systems. These chips power intelligent vehicles and industrial robots, providing the computational muscle for real-time sensing, decision-making, and process automation. Recent deployments in autonomous fleets have demonstrated significant gains in navigation accuracy and safety.
Security is also taking centre stage with the rise of secure enclaves and privacy-preserving chips. These chips are designed to counter emerging cyber threats and embed robust hardware-level protection to safeguard sensitive data. From mobile payments to confidential communications, they ensure data integrity and privacy, helping meet stringent compliance and security standards across industries.
Five new-age mantras
- Libraries and simulations at the core of chip innovation: As semiconductor technology advances, one key challenge is designing chips with smaller node sizes—such as those below 5nm. Shrinking geometries allow more transistors to be packed onto a chip, resulting in higher performance, reduced power consumption, and smaller form factors. However, achieving these benefits requires overcoming significant design and fabrication complexities. Key to this process is optimizing fabrication techniques and leveraging advanced simulation technologies, including Generative AI. As geometries shrink, traditional photolithography methods face physical limitations, demanding new patterning and process control approaches. A critical component of this development is semiconductor library creation and simulation. This involves building libraries of pre-characterized components—such as transistors and logic gates—with detailed data on timing, power, and behaviour under varying conditions (voltage, temperature, load, etc.). These libraries enable accurate circuit simulation and verification, ensuring the final chip performs reliably in real-world scenarios. Electronic Design Automation (EDA) tools play a central role by simulating chip behaviour using these libraries. The goal is to strike a balance between accuracy—to reflect real-world performance—and efficiency, so simulations remain scalable for large, complex designs. Modern libraries also account for advanced challenges such as timing variability, noise analysis, power integrity, leakage currents, and dynamic power behaviour.
- Material and simulation for scalable silicon: Selecting the optimal silicon node for a semiconductor device involves carefully balancing material selection and advanced simulation techniques. This ensures the final design meets performance targets while remaining manufacturable and cost-effective. As transistors shrink, physical limitations of silicon—such as reduced electron mobility and increased leakage currents—can degrade performance. To address these challenges, new materials are being introduced. High-k dielectrics like hafnium oxide improve gate capacitance, while two-dimensional materials such as graphene are being explored for their superior conductivity and scalability. Material selection directly impacts a device’s electrical, thermal, and mechanical properties, influencing its performance, reliability, and lifespan. Complementing material innovation, GenAI-powered simulation tools enable designers to virtually model and analyze material behavior and process interactions. These simulations help predict performance, optimize design, and refine fabrication processes before physical prototyping. They offer benefits, including process optimization, yield and throughput prediction, and faster time-to-market through AI-driven digital twins—ultimately reducing development cycles and improving product quality.
- Beyond Moore’s law: Advanced packaging, material innovation, and testability As Moore’s Law slows, innovation in semiconductor design is shifting beyond transistor scaling. Techniques like 3D stacking—using Through-Silicon Vias (TSVs) or micro bumps—enable vertical integration of multiple chips, reducing footprint while improving power delivery, thermal management, and signal integrity. Architectures such as System-in-Package (SiP) and chiplets further enhance functionality by integrating specialized logic, memory, and I/O blocks within compact packages. However, these advancements introduce new challenges in testability. Limited access to individual dies and low pin counts restricts the number of test pins, reducing bandwidth for test pattern application and potentially increasing test time. In advanced packaging with smaller geometries, designing for testability becomes critical due to increased complexity and the need for high-quality, cost-effective testing. Strategies like reduced pin count testing (RPCT) and design-for-testability (DFT) techniques—such as scan insertion and compression—help maintain test coverage and reduce data volume and application time. In 2.5D and 3D stacked chips, strategic test-point insertion improves observability and controllability of internal nodes, enhancing fault detection. Redistribution Layers (RDLs)—additional metal and dielectric layers—are used to reroute pads for simplified chip-to-chip bonding. Meanwhile, GenAI-powered EDA tools are transforming the design process by enabling predictive analysis, optimizing test coverage, and solving scaling challenges faster and more efficiently.
- Optimizing low geometry chips with AI-powered EDA: As semiconductor geometries continue to shrink, chip design demands hyper-convergent design flows that provide unified, system-level analysis—especially for multi-die architectures pushing beyond Moore’s Law. AI-enabled EDA tools are transforming this landscape by holistically optimizing PPA (power, performance, area) and automating repetitive tasks such as design space exploration, verification coverage, regression analytics, and test program generation. By centralizing and simplifying design flows, engineers can focus on innovation and seamlessly migrate complex chiplet-based designs across foundries and process nodes. With each node shrinking, workloads across all design stages—design verification, physical design, timing closure, DFT, and physical verification—increase significantly. The rise of EDA on the cloud is proving essential, offering scalability and compute elasticity that enable faster turnaround times and improved efficiency for complex, low-geometry designs.
- DFT practices for low geometry nodes: As transistor and I/O pin counts rise in advanced SoCs, testing complexity and cost increase. To maintain quality, test patterns and process cycles must evolve. Lower technology nodes face faults like processing defects, crystal imperfections, voltage issues, shorts, packaging flaws, transient and recurring faults, and delayed responses. These are worsened by high power density and heat dissipation, which can damage ICs. Mitigation strategies include clock gating and voltage shutoff, enhanced observability and controllability, monitoring output logic changes, and controlling input signals to detect faults effectively. As low-power design gains prominence, it introduces new challenges for design for testability (DFT), especially during automatic test pattern generation (ATPG), where power test access mechanisms help manage increased power dissipation during testing. Smart, power-conscious DFT strategies are essential to ensure fault coverage and reliability in next-gen chips.
Journey to transform
As companies navigate growing geopolitical tensions and supply chain complexities and adopt dynamic business models, the demand for low-geometry chips is accelerating. This demand is driven by the rise of High-Performance Computing (HPC), real-time edge processing, and AI-powered applications. These chips are becoming central to transformation strategies, enabling faster, smarter, and more efficient systems.
The convergence of five key focus areas—advanced packaging, material innovation, AI-enabled EDA, design for testability, and power-aware architectures—is unlocking new opportunities for business value creation and sustainable growth. Business leaders who invest early in HPC, edge, and AI performance transformations will gain a competitive edge, positioning their organizations to lead in the next-generation product journey.
