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Highlights
- Post‑quantum secure silicon combines cryptographic modernization with hardware security so chips and devices remain trustworthy even against quantum‑capable adversaries.
- This paper focuses on National Institute of Standards and Technology (NIST) standardized building blocks—key encapsulation and digital signatures—and how to integrate them into silicon, firmware, and protocols.
- The goal is practical adoption: start with pilots for one platform, define acceptance criteria, then scale to hybrid deployments and certification‑ready modules.
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Executive summary
Quantum‑resistant silicon must be planned now to protect long‑lived data and device trust.
Post‑quantum secure silicon combines cryptographic modernization with hardware security so chips and devices remain trustworthy even against quantum‑capable adversaries. Organizations face harvest‑now, decrypt‑later risk and growing guidance from standards bodies. This paper explains what secure silicon means, how post quantum cryptography (PQC) algorithms map into hardware and firmware, and what it takes to migrate protocols safely. The goal is practical adoption: start with pilots for one platform, define acceptance criteria, then scale to hybrid deployments and certification‑ready modules.
Definitions: secure silicon and PQC basics
Secure silicon embeds roots of trust and crypto engines; PQC adds algorithms that resist quantum attacks.
Secure silicon includes hardware roots of trust, secure boot, measured launch, key protection, secure update, and lifecycle monitoring. PQC covers public‑key mechanisms designed to resist quantum computing attacks. This paper focuses on NIST‑standardized building blocks—key encapsulation and digital signatures—and how to integrate them into silicon, firmware, and protocols. A key design principle is upgradeability: support algorithm agility so systems can evolve with standards, performance needs, and new threat findings.
Drivers and timelines: harvest‑now risk and mandates
The main driver is long‑term confidentiality and integrity under tightening timelines.
Customers are accelerating PQC plans due to data retention requirements, national guidance, and supplier mandates. Migration affects more than software: it includes boot chains, code signing, identity, and device attestation. Hybrid approaches (classical + PQC) are common during transition to preserve interoperability. Successful programs define a timeline, select priority assets, and align stakeholders across architecture, engineering, security, and compliance early.
Architecture: root of trust, PQC engines, lifecycle security
A layered security stack connects design‑time assurance to in‑field monitoring and response.
A reference architecture spans: secure design and verification; hardware trust anchors; PQC crypto engines; secure boot and update; protocol enablement for TLS/VPNs and code signing; device identity and attestation; telemetry for lifecycle integrity; and certification readiness. The architecture must address foundry‑to‑field integrity and supply‑chain assurance, including provenance and secure firmware appraisal. Practical implementation balances area, power, performance, and side‑channel resilience.
Roadmap: pilots to certification‑ready deployments
Start with pilots, then scale to hybrid deployments and certification‑ready modules.
Phase 1 (0–6 months): assessment, threat model, reference design, and a pilot integration of PQC KEM/signatures in silicon and firmware.
Phase 2 (6–18 months): deploy hybrid protocol support, expand test coverage, and prepare for module validation.
Phase 3 (18–36 months): harden against physical attacks, operationalize lifecycle telemetry, and complete compliance pathways. Throughout, adopt evidence‑driven testing for side‑channel and fault injection resilience, and maintain algorithm agility for future updates.