Industry
High Tech
High Tech Solutions to Drive Business Transformation through Technology
Highlights
- UCIe 3.0 doubles bandwidth with 48 GT/s and 64 GT/s data rates while maintaining full backward compatibility with UCIe 1.0/2.0.
- It helps overcome multi-vendor integration challenges through hybrid verification, co-design, attestation protocols, and ecosystem orchestration.
- It also delivers significantly faster time-to-market, lower design costs, improved yields, and scalable customisation in a true chiplet marketplace.
On this page
Executive summary
UCIe 3.0 unlocks the full potential of multi-vendor chiplet ecosystems and emerging marketplaces.
The semiconductor industry stands at a pivotal inflection point. Traditional monolithic System-on-Chip (SoC) designs are hitting the limits of Moore’s Law, power budgets, and cost scalability, especially in the era of explosive AI and high-performance computing (HPC) workloads. UCIe 3.0 (Universal Chiplet Interconnect Express 3.0), released in 2025, addresses these barriers by doubling maximum data rates to 48 GT/s and 64 GT/s while maintaining full backward compatibility with earlier versions.
This advancement enables true mix-and-match, multi-vendor chiplet ecosystems, unlocking unprecedented modularity, customisation, and faster time-to-market. It also paves the way for emerging chiplet marketplaces where intellectual property (IP) can be traded like commodities.
Introduction to the heterogeneous integration era.
Chiplets shift the paradigm from monolithic scaling to modular, multi-vendor designs.
For decades, semiconductor progress relied on shrinking transistors within a single monolithic die. However, the slowing of Moore’s Law, combined with skyrocketing design costs (often exceeding $500 million for advanced nodes) and power-density challenges, has shifted the paradigm toward heterogeneous integration.
Chiplets—smaller, specialised dies fabricated on optimal process nodes and packaged together—allow designers to mix compute, memory, I/O, and specialized accelerators from multiple vendors. This modular approach reduces risk, improves yield, and enables rapid customisation for AI, HPC, automotive, and edge applications. The Universal Chiplet Interconnect Express (UCIe) standard has emerged as the foundational open protocol for reliable, high-bandwidth die-to-die communication, evolving from UCIe 1.0/2.0 to the performance leap of UCIe 3.0.
Challenges in multi-vendor chiplet interoperability.
Real-world adoption faces significant technical and ecosystem hurdles despite UCIe 3.0’s advancements.
While the promise of chiplets is compelling, real-world adoption faces significant hurdles when integrating dies from different suppliers: die-to-die communication across varying process technologies and packaging types (2D, 2.5D, advanced 3D); protocol alignment and electrical compatibility; thermal and power management in densely packed multi-die systems; security and trust (verifying provenance, preventing tampering, and establishing hardware roots of trust); and supply-chain fragmentation with complex testing.
These challenges have historically slowed the shift to open chiplet ecosystems, particularly for performance-critical AI and HPC workloads. UCIe 3.0 delivers a transformative upgrade with support for 48 GT/s and 64 GT/s data rates, improved power efficiency, runtime recalibration, extended sideband reach (up to 100 mm), priority messaging, advanced manageability features, and full backward compatibility with UCIe 1.0 and 2.0.
Use Cases in AI accelerators and HPC
Multi-vendor chiplet integration delivers measurable value in real-world AI and HPC deployments.
Scalable GPU/TPU disaggregation allows hyperscalers to combine compute chiplets from one vendor with high-bandwidth memory and I/O chiplets from others, creating custom AI training clusters with terabyte-scale interconnect bandwidth. Custom AI SoCs for hyperscalers and enterprise enable rapid assembly of domain-specific accelerators (e.g., inference, training, vision) tailored to workload requirements while maintaining cost efficiency.
Early adopters in data centres and supercomputing are already piloting UCIe 3.0-based designs to overcome monolithic scaling limits. These use cases demonstrate higher performance, better power efficiency and thermal performance, improved customisation and scalability, and greater supply-chain resilience through access to best-in-class IP from multiple vendors.
Future outlook and recommendations
UCIe 3.0 will drive the next wave of tighter integration and fully open chiplet marketplaces.
Looking ahead, UCIe 3.0 will evolve toward tighter 3D and 2.5D integration, hybrid bonding, and fully open chiplet marketplaces supported by standardised testing and security profiles. By 2028–2030, chiplet-based designs are expected to dominate high-performance silicon, driven by AI’s massive demand for compute density and energy efficiency.
Enterprises and semiconductor firms should: build UCIe 3.0-ready design flows and verification environments today; pilot multi-vendor chiplet integrations with trusted partners; and invest in security and attestation capabilities to ensure trust in open ecosystems. Partnering with TCS for co-design, secure integration, testing, and ecosystem orchestration helps de-risk adoption and accelerate value realisation in the chiplet era.